The present disclosure relates generally to circuit design testing, and more specifically, to a physically aware scan diagnostic and power saving circuit insertion.
A scan chain is a technique used in design for testing the topology of an integrated circuit (IC) in order to make testing easier by providing a simple way to set and observe every flip-flop/latch in the IC. Scan diagnostic logic insertion is generally required in order to diagnose failing scan chains, and scan fails are a significantly large percentage of IC fails throughout the life of the product. Difficulties in isolating specific structures arise because of the overhead required to perform the failure analysis. Resolution down to the exact failing latch position could be made possible through diagnostic logic insertion at every single latch position, but this would be inefficient and impractical. Realistically, scan diagnostic logic can only be placed on a small fraction of the existing scan nets on an IC, and for successful failure analysis, generally only a small limited area of localization is required as there are trade-offs between the diagnostic resolution size and the scan diagnostic logic overhead.
Long scan nets in the scan chain create other additional concerns during scan chain analysis. They are a significant contributor to the consumption of functional chip power when allowed to switch during the functional operation of the chip, and power is generally consumed when not in a scanning mode by these long scan nets adding to the overall inefficiency of the scan chain analysis. Additionally, long scan nets are likely to have defects due to their large critical area and the number of shapes they occupy.